These are the OP CODES for the instruction set of INTEL MCS-48 MPUs, which includes 8048s, 8040s, 8049s, 8038s, and 8050s. If you want to learn more than you could ever hope to use about these chips, get the INTEL "Embedded Controller Handbook, vol.1" from Jameco. (look in BYTE for their ads).››00 NOP›01*›02 OUTL BUS,A [typical format....OUTput Accumulator to the BUSs. Destination first, then Source.]›03 ADD A,#data 2 [the trailing "2" signifies a 2 byte instruction. the "#data" is an immediate (follows the op code in memory) operand. this instruction, therefore, adds "#data" to the Accumulator.]›04 JMP 0 2 [the "0" sets the 256 byte page that you want to jump into. note that this is a two byte instruction - the second byte specifies the low order portion of the jump-to address.]›05 EN I [special op - Enable Interrupts.]›06* [no operation defined for this value.]›07 DEC A›08 INS A,BUS›09 IN A,P0 [INput Port 0 to the Accumulator. there are two general purpose ports, P0 and P1.›0A IN A,P1›0B*›0C MOVD A,P4 [these ports (4-7) require an extra chip.]›0D MOVD A,P5›0E MOVD A,P6›0F MOVD A,P7›10 INC @R0 ["@R0" denotes an indirect address into data memory, using R0 as an address register. in 6502 terms, thus - INC ($82).]›11 INC @R1›12 JB0 2›13 ADDC A,#data 2›14 CALL 0 2›15 DIS I›16 JTF 2›17 INC A›18 INC R0›19 INC R1›1A INC R2›1B INC R3›1C INC R4›1D INC R5›1E INC R6›1F INC R7›20 XCH A,@R0›21 XCH A,@R1›23 MOV A,#data 2›24 JMP 1 2›25 EN TCNTI›26 JNT0 2›27 CLR A›28 XCH A,R0›29 XCH A,R1›2A XCH A,R2›2B XCH A,R3›2C XCH A,R4›2D XCH A,R5›2E XCH A,R6›2F XCH A,R7›30 XCHD A,@R0›31 XCHD A,@R1›32 JB1 2›33*›34 CALL 1 2›35 DIS TCNTI›36 JT0 2›37 CPL A›38*›39 OUT P1,A›3A OUT P2,A›3B*›3C MOVD P4,A›3D MOVD P5,A›3E MOVD P6,A›3F MOVD P7,A›40 ORL A,@R0›41 ORL A,@R1›42 MOV A,T›43 ORL A,#data 2›44 JMP 2 2›45 STRT CNT›46 JNT1 2›47 SWAP A›48 ORL A,R0›49 ORL A,R1›4A ORL A,R2›4B ORL A,R3›4C ORL A,R4›4D ORL A,R5›4E ORL A,R6›4F ORL A,R7›50 ANL A,@R0›51 ANL A,@R1›52 JB2 2›53 ANL A,#data 2›54 CALL 2 2›55 STRT T›56 JT1 2›57 DA A›58 ANL A,R0›59 ANL A,R1›5A ANL A,R2›5B ANL A,R3›5C ANL A,R4›5D ANL A,R5›5E ANL A,R6›5F ANL A,R7›60 ADD A,@R0›61 ADD A,@R1›62 MOV T,A›63*›64 JMP 3 2›65 STOP TCNT›66*›67 RRC A›68 ADD A,R0›69 ADD A,R1›6A ADD A,R2›6B ADD A,R3›6C ADD A,R4›6D ADD A,R5›6E ADD A,R6›6F ADD A,R7›70 ADDC A,@R0›71 ADDC A,@R1›72 JB3 2›73*›74 CALL 3 2›75 ENT0 CLK›76 JF1 2›77 RR A›78 ADDC A,R0›79 ADDC A,R1›7A ADDC A,R2›7B ADDC A,R3›7C ADDC A,R4›7D ADDC A,R5›7E ADDC A,R6›7F ADDC A,R7›80 MOVX A,@R0›81 MOVX A,@R1›82*›83 RET›84 JMP 4 2›85 CLR F0›86 JNI 2›87*›88 ORL BUS,#data 2›89 ORL P1,#data 2›8A ORL P2,#data 2›8C ORLD P4,A›8D ORLD P5,A›8E ORLD P6,A›8F ORLD P7,A›90 MOVX @R0,A›91 MOVX @R1,A›92 JB4 2›93 RETR [return from a call (which is just a JSR).]›94 CALL 4 2›95 CPL F0›96 JNZ 2›97 CLR C›98 ANL BUS,#data 2›99 ANL P1,#data 2›9A ANL P2,#data 2›9B*›9C ANLD P4,A›9D ANLD P5,A›9E ANLD P6,A›9F ANLD P7,A›A0 MOV @R0,A›A1 MOV @R1,A›A2*›A3 MOVP A,@A›A4 JMP 5 2›A5 CLR F1›A6*›A7 CPL C›A8 MOV R0,A›A9 MOV R1,A›AA MOV R2,A›AB MOV R3,A›AC MOV R4,A›AD MOV R5,A›AE MOV R6,A›AF MOV R7,A›B0 MOV @R0,#data 2›B1 MOV @R1,#data 2›B2 JB5 2›B3 JMPP @A›B4 CALL 5 2›B5 CPL F1›B6 JF0 2›B7*›B8 MOV R0,#data 2›B9 MOV R1,#data 2›BA MOV R2,#data 2›BB MOV R3,#data 2›BC MOV R4,#data 2›BD MOV R5,#data 2›BE MOV R6,#data 2›BF MOV R7,#data 2›C0*›C1*›C2*›C3*›C4 JMP 6 2›C5 SEL RB0›C6 JZ 2›C7 MOV A,PSW›C8 DEC R0›C9 DEC R1›CA DEC R2›CB DEC R3›CC DEC R4›CD DEC R5›CE DEC R6›CF DEC R7›D0 XRL A,@R0›D1 XRL A,@R1›D2 JB6 2›D3 XRL A,#data 2›D4 CALL 6 2›D5 SEL RB1›D6*›D7 MOV PSW,A›D8 XRL A,R0›D9 XRL A,R1›DA XRL A,R2›DB XRL A,R3›DC XRL A,R4›DD XRL A,R5›DE XRL A,R6›DF XRL A,R7›E0*›E1*›E2*›E3 MOVP3 A,@A›E4 JMP 7 2›E5 SEL MB0›E6 JNC 2›E7 RL A›E8 DJNZ R0 2 [Decrement and Jump if Not Zero..... nice!]›E9 DJNZ R1 2›EA DJNZ R2 2›EB DJNZ R3 2›EC DJNZ R4 2›ED DJNZ R5 2›EE DJNZ R6 2›EF DJNZ R7 2›F0 MOV A,@R0›F1 MOV A,@R1›F2 JB7 2›F3*›F4 CALL 7 2›F5 SEL MB1›F6 JC 2 2›F7 RLC A›F8 MOV A,R0›F9 MOV A,R1›FA MOV A,R2›FB MOV A,R3›FC MOV A,R4›FD MOV A,R5›FE MOV A,R6›FF MOV A,R7››VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV